The present invention relates to the technology of semiconductor integrated circuit (IC) devices.
There is a semiconductor integrated circuit device which, as shown in FIG. 7, has two stacked semiconductor IC chips 71 and 72. Pads of the lower semiconductor IC chip 71 are arranged in the order of address pad 171A, input/output (I/O) pad 171B, and I/O pad 171C. Pads of the upper semiconductor IC chip 72 are arranged in the order of address pad 172A, I/O pad 172B, I/O pad 172C, and address pad 172D.
In connecting the semiconductor IC chips 71 and 72 with a lead frame 73 having an address lead electrode 73a, an I/O lead electrode 73b, an I/O lead electrode 73C, and an address lead electrode 73d by wire-bonding method, the arrangement of the pads of the upper semiconductor IC chip 72 should be consistent with the arrangement of the pads of the lower semiconductor IC chip 71. If the pads of the upper semiconductor IC chip 72 are arranged in consistence with the pads of the lower semiconductor IC chip 71, wiring of the upper semiconductor IC chip 72 can be accomplished by performing wiring with reference to the pad arrangement of the lower semiconductor IC chip 71. In this case, even though there is a difference in the number of address pins, the number of I/O pins, and/or the number of control pins between the two chips due to a difference in the capacity and the kind of the devices, there is no problem so long as the pad arrangements of the two chips are consistent with each other.
However if, as shown in FIG. 8, a semiconductor IC chip 82 laid on the lower semiconductor IC chip 71 has pads arranged in the order different from the pads of the latter, namely, the pads 182A-182D of the semiconductor IC chip 82 are arranged in the order of I/O pad 182A, address pad 182B, address pad 182C, and I/O pad 182D, it follows that conductive wires extending from the upper semiconductor IC chip 82 to the lead frame 73 cross each other. Thus wiring for the upper chip is impossible and the two chips cannot be formed as a composite memory, for example.
As described above, in the case where the arrangement of the pads of the upper device and that of the pads of the lower device are different from each other, wire bonding between the lower chip and the lead frame is accomplished properly, but the wires extending between the upper chip and the lead frame cross each other and defective continuity occurs. Consequently, it is impossible to accomplish wiring between the upper chip and the lead frame, so that a composite device cannot be obtained.
If wire bonding is performed with reference to the upper chip, i.e., a lead frame that does not cause crossing of the wires extending between the upper chip and the lead frame is used, then the wires extending between the lower chip and the lead frame cross each other, and defective continuity occurs therebetween. Consequently, it is impossible to accomplish wiring between the lower chip and the lead frame.
If the upper and lower chips have similar or mutually consistent pad arrangements but the upper chip is much smaller than the lower chip, it follows that wires between the upper chip and the lead frame are necessarily long. In this case, in packaging the upper chip and lower chip with molding resin, the long conductive wires would be displaced by the molding resin and defective continuity occurs.
In a semiconductor IC device disclosed in Japanese Patent Application Laid-Open No. 3-178140, relay electrodes are provided on a silicon substrate on which a semiconductor IC chip is placed. Chip electrodes are connected to the respective relay electrodes with a conductive wire, and then the relay electrodes are connected to respective inner leads with a conductive wire, whereby the conductive wires are shortened to prevent occurrence of defective continuity thereof. However because the Japanese Patent Application Laid-Open No. 3-178140 does not deal with a composite device, the problem of different pad arrangements between the upper and lower chips is not considered therein.
Therefore, it is an object of the present invention to provide a semiconductor IC device allowing optimum wiring to be accomplished for first and second semiconductor IC chips so that both chips are formed into a composite device.
To achieve the object, a semiconductor integrated circuit device of the present invention comprises:
a first semiconductor integrated circuit chip having a plurality of first electrodes;
a second semiconductor integrated circuit chip mounted on the first semiconductor integrated circuit chip and having a plurality of second electrodes;
a package sealing the first and second semiconductor integrated circuit chips;
a lead frame electrically connected to the first electrodes via the respective first conductive wires;
a plurality of relay electrodes provided on the first semiconductor integrated circuit chip;
a plurality of second conductive wires electrically connecting one end of each of the relay electrodes and the respective second electrodes to each other; and
a plurality of third conductive wires electrically connecting the other end of each of the relay electrodes and the lead frame to each other,
wherein no one of the second conductive wires crosses another one of the other second conductive wires and no one of the third conductive wires crosses another one of the third second conductive wires.
The first electrodes may have attributes different from one another, and the second electrodes have attributes different from one another, and an arrangement of the attributes of the first electrodes and that of the attributes of the second electrodes may be different from each other.
In the semiconductor integrated circuit device, wire bonding between the first and second semiconductor integrated chips and the lead frame is carried out such that the first and second electrodes of the same attribute are connected to an identical corresponding lead of the lead frame. More specifically, the first electrodes are electrically connected to the lead frame via the first conductive wires, while the second electrodes are electrically connected to the one end of the relay electrodes via the respective second conductive wires, and the other end of each relay electrode is electrically connected to the lead frame via the third conductive wires. At this time, if the relay electrodes have an appropriate pattern, the second conductive wires do not cross each other and the third conductive wires also do not cross each other even when the arrangement or sequence of the attributes of the first electrodes is different from that of the attributes of the second electrodes. Thus, defective continuity between the second semiconductor integrated circuit chip and the lead frame is avoided. That is, even if the arrangement of the attributes of the first electrodes is different from that of the attributes of the second electrodes, optimum wiring can be accomplished for the first and second semiconductor integrated circuit chips. Thus, the first and second semiconductor integrated circuit chips can be formed into a composite device.
Even though there is a big difference in size between the first semiconductor integrated circuit chip and the second semiconductor integrated circuit chip, neither the second wires nor the third wires are prevented from being too long because the one end of the relay electrodes and the second electrodes are electrically connected via the respective second conductive wires, and the other end of the relay electrodes and the lead frame are electrically connected via the respective third conductive wires. Therefore when the package is formed by molding resin, the second electrodes and the third electrodes are prevented from being displaced or moved by the molding resin. Thus, defective continuity between the second semiconductor integrated circuit chip and the lead frame is prevented. That is, even though there is a big difference in size between the first semiconductor integrated circuit chip and the second semiconductor integrated circuit chip, optimum wiring can be accomplished for the first and second semiconductor integrated circuit chips. Thus, the first and second semiconductor integrated circuit chips can be formed as a composite device.
In one embodiment, the first electrodes are arranged along an edge of the first semiconductor integrated circuit chip, while the second electrodes are arranged along an edge of the second semiconductor integrated circuit chip approximately parallel with the edge of the first semiconductor integrated circuit chip. And, at least one of the relay electrodes has at least one bent portion so that the ends of the at least one relay electrode are placed in different positions relative to a direction parallel to the edge of the first or second semiconductor integrated circuit chip. This construction makes it possible to dispose one end of each relay electrode adjacent to the associated second electrode, while disposing the other end of each relay adjacent to the first electrode corresponding to the second electrode.
Alternatively, each relay electrode may be oblong or rectangular and extends in a direction intersecting the edge of the first semiconductor integrated circuit chip.
In one embodiment, the relay electrodes comprise at least two first conductive layers disposed at an upper-surface side thereof, a second conductive layer disposed at a lower level than the first conductive layers, and a connection part for electrically connecting the first conductive layers and the second conductive layer to each other.
That is, the relay electrodes are three-dimensional. Thus, even if the relay electrodes are complicated in the configuration and disposition thereof, it is possible to prevent them from crossing each other and being electrically connected to each other.
In one embodiment, the first conductive layers and the second conductive layer are be made of metal. Since the first conductive layers disposed at the upper-surface side of the relay electrodes are made of metal, wire bonding can be carried out on the first conductive layers.
In one embodiment, the first electrodes are arranged along an edge of the first semiconductor integrated circuit chip, while the second electrodes are arranged along an edge of the second semiconductor integrated circuit chip approximately parallel with the edge of the first semiconductor integrated circuit chip. The first conductive layers of each relay electrode are oblong and extend in a direction intersecting the edge of the first semiconductor integrated circuit chip, and the second conductive layer of each relay electrode is oblong and extends in a direction intersecting the first conductive layers. The connection part is provided at each intersection between the first and second conductive layers.
With the above arrangement, one of the two first conductive layers is allowed to be disposed adjacent to the associated second electrode, and the other of the two first conductive layers is allowed to be disposed adjacent to the first electrode corresponding to the second electrode.